Perfect Patrick! I will compiled ISE libs with the new GHDL script
version ;)
---
CARLOS ALBERTO RUIZ NARANJO
_FPGA engineer_
***@dasphotonics.com
__
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www.dasphotonics.com [3]
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On 27-10-2016 23:21, Patrick Lehmann wrote:
> Hello Carlos,
>
> I pushed a commit to add '-CoreLib' and '--corelib' to the scripts.
>
> The pull request is filed here: https://github.com/tgingold/ghdl/pull/178?ts=2 [1]
>
> I can't see any failing files. In Windows or Linux.
>
> Kind regards
>
> Patrick
>
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> FROM: Ghdl-discuss [mailto:ghdl-discuss-***@gna.org] ON BEHALF OF Carlos Alberto Ruiz
> SENT: Tuesday, October 25, 2016 5:03 PM
> TO: GHDL discuss list <ghdl-***@gna.org>
> SUBJECT: Re: [Ghdl-discuss] Problems with XilinxCoreLib
>
> I have compile unimacro with GHDL script and xilinxcorelib and unisim with Stefan script.
>
> Thanks to Stefan and Patrick :)
>
> I have a doubt, can I use the compile libraries with VHDL 93 in a VHDL 2000 project?
>
> ---
>
> CARLOS ALBERTO RUIZ NARANJO
> _FPGA engineer_
> ***@dasphotonics.com
>
> __
>
> _DAS PHOTONICS S.L. _
> _Ciudad Politécnica de la Innovación, Camino de Vera s/n._
> _Acceso K, Edificio 8F, 2ª planta 46022 Valencia - SPAIN_
> _Telf: +34 963 556 150 - Directo: +34 --------------_
>
> _www.dasphotonics.com [3]_
>
> _Before printing this email think well whether it is really necessary._
> _This e-mail contains confidential information.It is for the intended recipient only. If you are not the intended recipient of this e-mail, please notify the author by replying to this e-mail immediately and delete the message from your computer. If you are not the intended recipient you must not use, disclose, distribute, copy, print or rely on this e-mail_
>
> On 25-10-2016 16:39, Carlos Alberto Ruiz wrote:
>
> Thanks for the response Andrey Gursky.
>
> I use VHDL 2000. Im having errors in a lot of ports. For example:
>
> signal in_0 : std_logic;
>
> signal out_0 : std_logic';
>
> signal out_1 : std_logic';
>
> IP0: ip0 port map (
> input => in_0 & in_0, -- ERROR
> output => out_0
> );
>
> IP1: ip1 port map (
> input => out_0 and out_0, -- ERROR
> output => out_1
> );
>
> I canÂŽt put expression in ports. Is there any way you could do it? I have a really big design and is very tedious change everything.
>
> I want to use GHDL with VUNIT, so I would not change compiler.
>
> CARLOS ALBERTO RUIZ NARANJO
> _FPGA engineer_
> ***@dasphotonics.com
>
> __
>
> _DAS PHOTONICS S.L. _
> _Ciudad Politécnica de la Innovación, Camino de Vera s/n._
> _Acceso K, Edificio 8F, 2ª planta 46022 Valencia - SPAIN_
> _Telf: +34 963 556 150 - Directo: +34 --------------_
>
> _www.dasphotonics.com [3]_
>
> _Before printing this email think well whether it is really necessary._
> _This e-mail contains confidential information.It is for the intended recipient only. If you are not the intended recipient of this e-mail, please notify the author by replying to this e-mail immediately and delete the message from your computer. If you are not the intended recipient you must not use, disclose, distribute, copy, print or rely on this e-mail_
>
> On 25-10-2016 14:59, Andrey Gursky wrote:
>
> Hi,
>
> On Tue, 25 Oct 2016 14:19:49 +0200
> Carlos Alberto Ruiz <***@dasphotonics.com> wrote:
>
> Hello,
>
> I have this error to compile:
>
> /home/cruiz/ELINT/95512010_FPGA_central/src/tosca2/tosca2_ifc_suser_elint_agsw.vhd:2078:58:
> actual expression must be globally static
>
> In this line:
>
> port map(id_ch1 => i_fmc1(0,7) & i_fmc1(0,6) & i_fmc1(0,5) &
> i_fmc1(0,4)
> & i_fmc1(0,3) & i_fmc1(0,2) & i_fmc1(0,1) & i_fmc1(0,0),
>
> I have the same problem in Xilins, but its only a waring.
>
> Are you sure, the expression is indeed globally static?
>
> From my experience [1], Xilinx warns you about violating the VHDL
> standard (by the way, what version do you use?), though such standard's
> constraints are really artificial and have been overcome many years ago
> by proprietary vendors such as Xilinx and Altera, but unfortunately not
> GHDL. At least the issue I've encountered could be easy fixed in
> another VHDL simulator [2].
>
> Regards,
> Andrey
>
> [1] relax "choice must be locally static expression"
> https://sourceforge.net/p/ghdl-updates/tickets/40/ [4]
>
> [2] VHDL compiler and simulator
> https://github.com/nickg/nvc [5]
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Links:
------
[1] https://github.com/tgingold/ghdl/pull/178?ts=2
[2] http://vlsi-eda.inf.tu-dresden.de/
[3] http://www.dasphotonics.com/
[4] https://sourceforge.net/p/ghdl-updates/tickets/40/
[5] https://github.com/nickg/nvc
[6] https://mail.gna.org/listinfo/ghdl-discuss